﻿/**
  ******************************************************************************
  * @file    Libraries/Device/JS32T031/JS32T031_LL_Driver/inc/js32t031_ll_sysctrl.h
  * @author  JUSHENG Application Team
  * @version V1.0.0
  * @date    02-19-2022
  * @brief   This file contains all the SYSCTRL LL firmware functions.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT 2022 JUSHENG</center></h2>
  *
  *
  *
  ******************************************************************************
  */ 
  
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __JS32T031_LL_SYSCTRL_H
#define __JS32T031_LL_SYSCTRL_H

#ifdef __cplusplus
 extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "js32t031.h"
     
/** @addtogroup JS32T031_StdPeriph_Driver JS32T031 Driver
  * @{
  */
     
/** @addtogroup sysctrl_interface_gr SYSCTRL Driver
  * @ingroup  JS32T031_StdPeriph_Driver
  * @{
  */ 

/** @addtogroup SYSCTRL_LL_Driver SYSCTRL LL Driver
  * @ingroup  sysctrl_interface_gr
  * @brief Mainly the driver part of the SYSCTRL module, which includes \b SYSCTRL \b Register 
  * \b Constants, \b SYSCTRL \b Exported \b Constants, \b SYSCTRL \b Exported \b Struct, \b SYSCTRL
  * \b Data \b transfers \b functions, \b SYSCTRL \b Initialization \b and \b SYSCTRL \b Configuration 
  * \b And \b Interrupt \b Handle \b function.
  * @{
  */

/* Exported types ------------------------------------------------------------*/

/* Exported constants --------------------------------------------------------*/

/** @defgroup SYSCTRL_LL_Register_Constants SYSCTRL LL Register Constants
  * @ingroup  SYSCTRL_LL_Driver
  * @brief    SYSCTRL LL register constant table definition
  *
  *
@verbatim   
  ===============================================================================
                                Register Constants
  ===============================================================================  
  
    Register Constants mainly encapsulates each bit in each group in the SYSCTRL 
    register. In the process of configuration, the macro definition can be directly 
    called to configure the SYSCTRL register, mainly for convenience. Understand the 
    configuration of the SYSCTRL.
    
@endverbatim
  *
  * @{
  */

/***** SYSTEM Register ********/


/* configure SYS_CON0 regiter */
/*! RW, Fast release reset enable
 * 0: disable
 * 1: enable
 */
#define LL_SYSCTRL_CON0_FAST_RST_EN                                         (1UL << 31)

/*! RW, Not reset when port wake up from sleep
 * 0: disable
 * 1: enable
 */
#define LL_SYSCTRL_CON0_SLEEP_GOON_EN                                       (1UL << 30)

/*! RW, Delay several sysclk to wakeup from sleep by port  
 * param: n can be 0~7
 */
#define LL_SYSCTRL_CON0_SLEEP_DLY_CNT(n)                                    (((n)&0x7) << 27)

/*! RW, reset GPIO debounce relative configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_DBS_SOFT_RST                                        (1UL << 26)

/*! RW, reset CRC relative configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_CRC_SOFT_RST                                        (1UL << 25)

/*! RW, reset UST0 relative configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_UST0_SOFT_RST                                       (1UL << 22)

/*! RW, reset GPIOA/GPIOB/GPIOC/GPIOD/GPIOE configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_GPIO_SOFT_RST                                       (1UL << 20)

/*! RW, reset KeyADC configure register  
 *0: reset  
 *1: finish reset  
*/
#define LL_SYSCTRL_CON0_ADC_SOFT_RST                                        (1UL << 19)

/*! RW, reset UART1 relative configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_UART1_SOFT_RST                                      (1UL << 18)

/*! RW, reset UART0 relative configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_UART0_SOFT_RST                                      (1UL << 17)

/*! RW, reset SPI0 relative configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_SPI_IIC0_SOFT_RST                                   (1UL << 15)

/*! RW, reset LCD relative configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_LCD_SOFT_RST                                        (1UL << 12)

/*! RW, reset TIMERs relative configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_TIMER_SOFT_RST                                      (1UL << 6)

/*! RW, reset TK relative configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_TK_SOFT_RST                                         (1UL << 0)


/******** configure SYS_CON1 regiter **********/

/*! RW, LED function control  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CON1_LED_AEN                                             (1UL << 31)

/*! RW, Multiply LED current by 1.5 times  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CON1_LED_ISELX                                           (1UL << 30)

/*! RW, LED current divided by 2  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CON1_LED_ISELD                                           (1UL << 29)

/*! RW, Pa15 (SWD) was selected as UART1_TX function  
 * 0: diasble
 * 1: enable
 (Turn off the SWD function when using)
 */
#define LL_SYSCTRL_CON1_UART1_SYS_EN1                                       (1UL << 19)

/*! RW, Pa14 (SWD) was selected as UART1_RX function  
 * 0: diasble
 * 1: enable
 (Turn off the SWD function when using)
 */
#define LL_SYSCTRL_CON1_UART1_SYS_EN0                                       (1UL << 18)

/*! RW, Cp mode select mclr io  
 * 0: diasble
 * 1: enable
 */
#define LL_SYSCTRL_CON1_CP_MCLR_IO_SEL                                      (1UL << 17)

/*! RW, The watchdog automatically shuts off when it enters sleep/ Stop mode  
 * 0: diasble  
 * 1: enable  
 */
#define LL_SYSCTRL_CON1_WDT_LP_GATE_EN                                      (1UL << 13)

/*! RW, Stop some functions during debug mode
 * 0: stop 
 * 1: permit
 */
#define LL_SYSCTRL_CON1_DEBUG_EN                                            (1UL << 12)

/*! RW, Remap interrupt entrance address from Eflash to SRAM.0-192Bytes  
 * 0: interrupt entrance address location at Eflash  
 * 1: interrupt entrance address location at SRAM 
 */
#define LL_SYSCTRL_CON1_INT_REMAP_EN                                        (1UL << 11)

/*! RW, NMI Pin polarity inverse choose  
 * 0: high level pin trigger NMI  
 * 1: low level pin trigger NMI  
 */
#define LL_SYSCTRL_CON1_NMI_INV_SEL                                         (1UL << 10)

/*! RW, xosc as sys_clk in cp_mode  
 * 0: diasble  
 * 1: enable  
 */
#define LL_SYSCTRL_CON1_CP_MODE_SYSCLK_EN                                   (1UL << 9)

/*! RW, enable or disable SWD mode  
 * 0: diasble  
 * 1: enable  
 */
#define LL_SYSCTRL_CON1_SWD_EN                                              (1UL << 8)

/*! RW, VCC low voltage detecter quickly reset GPIO status register  
 * 0: diasble  
 * 1: enable  
 */
#define LL_SYSCTRL_CON1_LVDVCC_WKUP_EN                                      (1UL << 7)

/*! RW, Enable system bus access out of side memory zone return error response  
 * 0: diasble  
 * 1: enable  
 */
#define LL_SYSCTRL_CON1_SYS_ERR_RESP_EN                                     (1UL << 5)

/*! RW, Enable system bus access out of side memory zone trigger NMI interrupt  
 * 0: diasble  
 * 1: enable  
 */
#define LL_SYSCTRL_CON1_SYS_ERR_INT_EN                                      (1UL << 4)

/*! RW, Enable PA10 as external NMI input to CPU  
 * 0: diasble  
 * 1: enable  
*/
#define LL_SYSCTRL_CON1_NMI_INT_EN                                          (1UL << 1)

/*! RW, Enable system lockup trigger system reset  
 */
#define LL_SYSCTRL_CON1_LOCKUP_EN                                           (1UL << 0)


/********** configure SYS_CON2 regiter *********/
/*! RW, PortB debounce enable register [13:0] for PB13-PB0  
 * n pb13~pb0 bit map  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CON2_PB_DEB_EN(n)                                        (((n) & 0x3FFF) << 16)

/*! RW, PortA debounce enable register [15:0] for PA15-PA0  
 * n pa15~pa0 bit map  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CON2_PA_DEB_EN(n)                                        (((n) & 0xFFFF) << 0)

/********** configure SYS_CON3 regiter *********/

/*! RW, Internal LDO configuration options   
 * 0: with feedback  
 * 1: without feedback  
 */
#define LL_SYSCTRL_CON3_PMU_HPXCPFB                                         (1UL << 30)

/*! RW, PB current mode, used when driving LED  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CON3_PB_CC(n)                                            (((n) & 0x3FFF) << 16)

/*! RW, PA current mode, used when driving LED  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CON3_PA_CC(n)                                            (((n) & 0xFFFF) << 0)

/************configure CLK_CON0 regiter*****************/
/*! RW, LCD clk select 
 * 00: HIRC_DIV_32K  
 * 01: LIRC_DIV_32K  
 * 10: reserved
 * 11: LIRC_256K  
 */
#define LL_SYSCTRL_CLK_CON0_LCD_CLK_SEL(n)                                  (((n) &0x3) << 20)

/*! RW, Lvd_deb_clk select 
 * 00: APB0_CLK  
 * 01: HIRC_CLK  
 * 10: HIRC_DIV2_CLK  
 * 11: LIRC_256K  
 */
#define LL_SYSCTRL_CLK_CON0_LVD_DEB_CLK_SEL(n)                              (((n) &0x3) << 16)

/*! RW, GPIO debouce work clock select  
 * 00: HIRC_CLK  
 * 01: LIRC_DIV_32K 
 * 10: SYSCLK  
 * 11: LIRC 256K   
 */
#define LL_SYSCTRL_CLK_CON0_GPIO_DEB_CLK_SEL(n)                             (((n) &0x3) << 6)

/*! RW, system clock select  
 * 00: LIRC 256K  
 * 01: XOSC  
 * 10: HIRC_CLK  
 * 11: HIRC_CLK  
 */
#define LL_SYSCTRL_CLK_CON0_SYSCLK_SEL(n)                                   (((n) &0x3) << 0)


/**************** configure CLK_CON1 regiter *****************/

/*! RW, HIRC clock divider  
 * 0x0: divide by 1  
 * 0x1: divide by 2  
 * ...  
 * 0x1e divide by 31  
 * 0x1f close HIRC divide clock  
 */
#define LL_SYSCTRL_CLK_CON1_TK_HCLK_DIV(n)                                  (((n) & 0x1F) << 19)

/*! RW, System clock divider  
 * 0x00: divide by 1  
 * 0x01: divide by 2  
 * ...  
 * 0x3e: divide by 63  
 * 0x3f: close sys_clk  
 */
#define LL_SYSCTRL_CLK_CON1_SYSCLK_DIV(n)                                   (((n) & 0x3F) << 0)


/****************configure CLK_CON2 regiter*************/

/*! RW, LCD clock enable  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_LCD_CLK_EN                                      (1UL << 26)

/*! RW, Enable CRC clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_CRC_CLK_EN                                      (1UL << 25)

/*! RW, Enable eflash erase/program clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_EFLASH_MEM_CLK_EN                               (1UL << 24)

/*! RW, Enable UST0 clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_UST0_CLK_EN                                     (1UL << 21)

/*! RW, Enable uart1 clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_UART1_CLK_EN                                    (1UL << 18)

/*! RW, Enable uart0 clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_UART0_CLK_EN                                    (1UL << 17)

/*! RW, Enable spi0 clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_SPI_IIC0_CLK_EN                                 (1UL << 15)

/*! RW, Enable TK clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_TK_CLK_EN                                       (1UL << 14)

/*! RW, LCD PCLK clock enablement  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_LCD_PCLK_EN                                     (1UL << 13)

/*! RW, Enable timer1 clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_TIMER1_CLK_EN                                   (1UL << 10)

/*! RW, Enable timer0 clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_TIMER0_CLK_EN                                   (1UL << 9)

/*! RW, Enable timer4 clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_TIMER4_CLK_EN                                   (1UL << 6)

/*! RW, Enable SRAM clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_SRAM0_CLK_EN                                    (1UL << 2)


/********************configure CLK_CON3 regiter****************/
/*! RO, HIRC enable syn flag  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON3_HIRC_EN_FLAG                                    (((SYSCTRL->CLK_CON3) >> 31) & 0x1)

/*! RW, Hrcosc frequency control selection(NVR TRIM)  
 * 0x00: lowest  
 * 0xfff: hightest  
 */
#define LL_SYSCTRL_CLK_CON3_HIRC_FSC(n)                                     (((n) & 0xFFF) << 18)

/*! RW, HIRC enable signal  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON3_HIRC_EN                                         (1UL << 17)

/*! RW, HIRC frequency control selection  
 * 00: 24MHz  
 * 01: 32MHz  
 * 10: 36MHz  
 * 11: 48MHz  
 */
#define LL_SYSCTRL_CLK_CON3_HIRC_FSEL(n)                                    (((n) & 0x3) << 10)

/*! RW, HIRC temperature compensation coefficient
 * param: n can be 0~0x7
 */
#define LL_SYSCTRL_CLK_CON3_HIRC_FTS(n)                                     (((n) & 0x7) << 7)

/*! RW, HIRC fine tune control (NVR TRIM)  
 * 0x00: lowest  
 * 0x1f: hightest  
 */
#define LL_SYSCTRL_CLK_CON3_HIRC_FFS(n)                                     (((n) & 0x1f) << 2)


/**************** configure SYS_ERR regiter ****************/
/*! RW, clock use error status.  
 */
#define LL_SYSCTRL_SYSERR0_CLK_ERR_PEND                                     (1UL << 1)

/*! get the clock use error pending  
 * 0: clock use error not happen  
 * 1: clock use error happens  
 */
#define LL_SYSCTRL_SYSERR0_CLK_ERR_PEND_GET(p_sysctrl)                      ((((p_sysctrl)->SYS_ERR0) >> 1) & 0x1)

/*! clear the pending which indicate the failure of external xosc  
 */
#define LL_SYSCTRL_SYSERR0_CLK_ERR_PEND_CLR(p_sysctrl)                      ((p_sysctrl)->SYS_ERR0 &= ~LL_SYSCTRL_SYSERR0_CLK_ERR_PEND)

/*! RW, Indicate the error pending of bus operation out of side memories.  
 * if set sys_err_int_en, this pending will make NMI interrupt happens  
 */
#define LL_SYSCTRL_SYSERR0_SYS_ERR_PEND                                     (1UL << 0)

/*! get the system error pending  
 * 0: system error not happen  
 * 1: system error happens  
 */
#define LL_SYSCTRL_SYSERR0_SYS_ERR_PEND_GET(p_sysctrl)                      ((((p_sysctrl)->SYS_ERR0) >> 0) & 0x1)

/*! clear the system error pending  
 */
#define LL_SYSCTRL_SYSERR0_SYS_ERR_PEND_CLR(p_sysctrl)                      ((p_sysctrl)->SYS_ERR0 &= ~LL_SYSCTRL_SYSERR0_SYS_ERR_PEND)


/**************** configure WKUP_CON0 regiter ****************/

/*! WO, Write 1 to clear the relative pending
 */
#define LL_SYSCTRL_WKUP_CON0_PEND_CLR(n)                                    (((n) & 0xF) << 24)

/*! Clear wake up all pending
 */
#define LL_SYSCTRL_WKUP_CON0_CLR_ALL_PEND                                   (0xF << 24)

/*! IO edge wake up sign
 * 0: No edge detected  
 * 1: Edge detected  
 */
#define LL_SYSCTRL_WKUP_CON0_WKUP_PEND                                      (0xF << 16)

/*! RO, Indicate the relative IO edge detected  
 *0: not detected  
 *1: detected  
*/
#define LL_SYSCTRL_WKUP_CON0_WAKEUP_PEND_GET(p_sysctrl)                     ((((p_sysctrl)->WKUP_CON0) >> 16) & 0xF)

/*! RW, Choose which edge to monitor of chosen external port  
 * 0: the rising edge  
 * 1: the falling edge  
 */
#define LL_SYSCTRL_WKUP_CON0_WKUP_EDGE_CHOOSE(n)                            (((n) & 0xF) << 8)

/*! RW, Enable monitor the edges change of chosen external port  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_WKUP_CON0_WKUP_EN(n)                                     (((n) & 0xF) << 0)


/***************** configure LP_CON0 regiter *****************/

/*! RW, Enable PMU_HPLDO、PMU_VI2EN、PMU_PUULDI_15V shut down  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_LP_CON0_PMU_LP_SW_EN                                     (1UL << 8)

/*! RW, Enable PMU_HPLDO、PMU_VI2EN、PMU_PUULDI_15V auto shut down when sleep
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_LP_CON0_PMU_LP_HW_EN                                     (1UL << 7)

/*! RW, Enable LIRC_256k
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_LP_CON0_RC256K_SOFT_EN                                   (1UL << 5)

/*! RW, Enable automatic shut down LIRC_256k when enter sleep mode  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_LP_CON0_RC256K_AUTO_DIS                                  (1UL << 4)

/*! RW, Enable automatic shut down HIRC,when stopclk or sleep mode  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_LP_CON0_HIRC_AUTO_DIS                                    (1UL << 3)

/*! RW, Enable automatic shut down sram CE when enter stopclk or sleep mode  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_LP_CON0_SRAM0_AUTO_DIS                                   (1UL << 2)

/*! RW, Stop clock mode
 * 0: not enter stop clock mode  
 * 1: enter stop clock mode  
 */
#define LL_SYSCTRL_LP_CON0_STOP_CLK_MODE                                    (1UL << 1)

/*! RW, sleep mode  
 * 0: not enter sleep mode  
 * 1: enter sleep mode  
 */
#define LL_SYSCTRL_LP_CON0_SLEEP                                            (1UL << 0)


/************* configure CHIPID_DCN regiter ********************/
/*! RO, Design change note version  
 * default: 0  
 */
#define LL_SYSCTRL_CHIPID_DCN_DCN_GET(p_sysctrl)                            ((((p_sysctrl)->CHIP_IDCN) >> 16) & 0xFF)

/*! RO, Chip id  
 * default: 0x2000  
 */
#define LL_SYSCTRL_CHIPID_DCN_ID_GET(p_sysctrl)                             ((((p_sysctrl)->CHIP_IDCN) >> 0) & 0xFFFF)


/************* configure PMU_CON0 regiter ********************/

/*! RW, Normal MODE BG VREF Voltage Control (EFALSH TRIM)
 * 0x0: minimum value  
 * 0x8: 1.218  
 * 0xf: maximum value  
 * Step = 6mV  
 */
#define LL_SYSCTRL_PMU_CON0_HP_VREF_SEL(n)                                  (((n) & 0xF) << 25)

/*! RW, Analog Block Bias current select
 * 0x0: Minimum  
 * 0xf: Maximum  
 */
#define LL_SYSCTRL_PMU_CON0_HP_V2I_SEL(n)                                   (((n) & 0xF) << 21)

/*! RW, Analog Block Bias current enable signal  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_PMU_CON0_HP_HPV2I_EN                                     (1UL << 20)

/*! RW, VDD LDO weak pull down resistance switch  
 * Only use in Normal LDO operate  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_PMU_CON0_HP_PDLI_EN                                      (1UL << 18)

/*! RW, VDD LDO pull-down resistance switch  
 * Only use in Normal LDO operate  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_PMU_CON0_HP_PDI_EN                                       (1UL << 17)

/*! RW, Low power Reference Current Control (EFALSH TRIM)  
 * 000: Minimum current  
 * 111: Maximum current  
 */
#define LL_SYSCTRL_PMU_CON0_LP_IREF_SEL(n)                                  (((n) & 0x7) << 14)

/*! RW, Normal power LDO enable signal  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_PMU_CON0_HP_LDO_EN                                       (1UL << 13)

/*! RW, Internal LDO enablement  
 * 0: disable   
 * 1: enable  
 */
#define LL_SYSCTRL_PMU_CON0_INNER_LDO_EN                                    (1UL << 12)

/*! RW, ULPBG VREF Voltage Control (EFALSH TRIM)  
 * 0x0: minimum value  
 * 0x8: 1.218  
 * 0xf: maximum value  
 * Step = 10mV  
 */
#define LL_SYSCTRL_PMU_CON0_LP_VREF_SEL(n)                                  (((n) & 0xF) << 8)

/*! RW, Deep sleep current switch  
 * 0: disable   
 * 1: enable  
 */
#define LL_SYSCTRL_PMU_CON0_LP_IDEEP                                        (1UL << 7)

/*! RW, Low power mode LDO Voltage Selection (EFLASH TRIM)  
 * 0x0: 1.50v  
 * 0x1: 1.45v  
 * 0x2: 1.55v  
 * 0x3: 1.60v  
 * 0x4: 1.65v  
 * 0x5: 1.75v  
 * 0x6: 1.85v  
 * 0x7: 1.25v  
 * Orthers: reserved  
 */
#define LL_SYSCTRL_PMU_CON0_LP_VDD_SEL(n)                                   (((n) & 0x7) << 4)

/*! RW, PMU low power acceleration  
 * 0: disable   
 * 1: enable  
 */
#define LL_SYSCTRL_PMU_CON0_LP_SSI                                          (1UL << 3)

/*! RW, NORMAL Power LDO Voltage Setting  
 * 0x0: 1.50v  
 * 0x1: 1.45v  
 * 0x2: 1.55v  
 * 0x3: 1.60v  
 * 0x4: 1.65v  
 * 0x5: 1.75v  
 * 0x6: 1.85v  
 * 0x7: 1.25v  
 * Orthers: reserved  
 */
#define LL_SYSCTRL_PMU_CON0_HP_VDD_SEL(n)                                   (((n) & 0x7) << 0)


/****************** configure RPCON regiter ******************/
/*! WO, Write 1 to clear lockup reset pending
 */
#define LL_SYSCTRL_RPCON_LOCKUP_RESET_PEND_CLR(p_sysctrl)                   ((p_sysctrl)->RPCON = (1UL << 18))

/*! WO, Write 1 to clear soft reset pending
 */
#define LL_SYSCTRL_RPCON_SOFT_RESET_PEND_CLR(p_sysctrl)                     ((p_sysctrl)->RPCON = (1UL << 17))

/*! WO, Write 1 to clear sleep_pending
 */
#define LL_SYSCTRL_RPCON_SLEEP_PEND_CLR(p_sysctrl)                          ((p_sysctrl)->RPCON = (1UL << 16))

/*! RO, When happen lockup reset, this bit will record this reset pending until cpu to clear it(ro).  
 * 0: not happen lockup reset  
 * 1: lockup reset have happend  
 */
#define LL_SYSCTRL_RPCON_LOCK_RESET_PEND_GET(p_sysctrl)                     ((((p_sysctrl)->RPCON) >> 2) & 0x1)

/*! RW, Write 1 to this bit will make chip to reset. which reset can make Eflash re-fetch NVR & main data.  
 * 0: not enable soft reset  
 * 1: enable soft reset  
 */
#define LL_SYSCTRL_RPCON_SOFT_RESET_PEND                                    (1UL << 1)

/*! get the soft reset chip pending  
 * 0: nothing happens  
 * 1: soft reset chip happens  
 */
#define LL_SYSCTRL_RPCON_SOFT_RESET_PEND_GET(p_sysctrl)                     ((((p_sysctrl)->RPCON) >> 1) & 0x1)

/*! RO, Write LP_CON[0] will record sleep mode pending even after port wakeup system reset.  
 */
#define LL_SYSCTRL_RPCON_SLEEP_PEND_GET(p_sysctrl)                          ((((p_sysctrl)->RPCON) >> 0) & 0x1)


/**************** configure PMUBK regiter ********************/
/*! RW, LOW Power LDO Voltage Setting backup  
 * use with LPCON[8:7]  
 * 0x0: 1.50v   
 * 0x1: 1.45v  
 * 0x2: 1.55v   
 * 0x3: 1.60v  
 * 0x4: 1.65v  
 * 0x5: 1.75v  
 * 0x6: 1.85v  
 * 0x7: 1.25v  
 * Orthers: reserved  
 */
#define LL_SYSCTRL_PMUBK_PMU_LLDOS(n)                                       (((n) & 0x7) << 4)

/**
  * @}
  */

/** @defgroup SYSCTRL_LL_Exported_Constants SYSCTRL LL Exported Constants
  * @ingroup  SYSCTRL_LL_Driver
  * @brief    SYSCTRL LL external constant definition
  *
@verbatim   
  ===============================================================================
                                Exported Constants
  ===============================================================================  
  
    Exported Constants mainly restricts the partial configuration of the abstraction 
    layer by using the form of enumeration to facilitate the use and understanding of 
    the module configuration. For the specific enumeration meaning, please refer to 
    the annotation of each module.

@endverbatim
  *
  * @{
  */
  
/***** DRIVER API *****/



/***** LL API *****/

/* set SYS_KEY regiter */
/*! Write 0x3fac87e4 to enable all system register write enable,Set sys_keyother value will  
 * clear this bitother value will clear this bit.Read return sys_key status  
 * 0:lock all system register wirte  
 * 1:unlock all system register write  
 */
#define LL_SYSCTRL_KEY_UNLOCK(p_sysctrl)                                  ((p_sysctrl)->SYS_KEY = 0x3fac87e4)
#define LL_SYSCTRL_KEY_LOCK(p_sysctrl)                                    ((p_sysctrl)->SYS_KEY = 0)


/***** LL API AND DRIVER API *****/

/**
  * @brief Enumeration constant for wake up group select
  */
typedef enum {
    /*! Set wake up group 0
     */
    LL_SYSCTRL_WKUP_0                = 0x1,
    /*! Set wake up group 1
     */
    LL_SYSCTRL_WKUP_1                = 0x2,
    /*! Set wake up group 2
     */
    LL_SYSCTRL_WKUP_2                = 0x4,
    /*! Set wake up group 3
     */
    LL_SYSCTRL_WKUP_3                = 0x8,
    /*! Set wake up group 4
     */
    LL_SYSCTRL_WKUP_4                = 0x10,
    /*! Set wake up group 5
     */
    LL_SYSCTRL_WKUP_5                = 0x20,
    /*! Set wake up group 6
     */
    LL_SYSCTRL_WKUP_6                = 0x40,
    /*! Set wake up group 7
     */
    LL_SYSCTRL_WKUP_7                = 0x80,
    /*! Set wake up group 8
     */
    LL_SYSCTRL_WKUP_8                = 0x100,
    /*! Set wake up group 9
     */
    LL_SYSCTRL_WKUP_9                = 0x200,
    /*! Set wake up group 10
     */
    LL_SYSCTRL_WKUP_10               = 0x400,
    /*! Set wake up group 11
     */
    LL_SYSCTRL_WKUP_11               = 0x800,
    /*! Set all wake up groups
     */
    LL_SYSCTRL_ALL_WKUP              = 0xFFF
} TYPE_ENUM_LL_WKUP;

/**
  * @brief Enumeration constant for which edge to monitor
  */
typedef enum {
    /*! Choose to monitor the rising edge
     */
    LL_SYSCTRL_WKUP_RISING                = 0,
    /*! Choose to monitor the falling edge
     */
    LL_SYSCTRL_WKUP_FALLING
} TYPE_ENUM_LL_WKUP_EDGE;


/**
  * @}
  */

/** @defgroup SYSCTRL_LL_Exported_Struct SYSCTRL LL Exported Struct
  * @ingroup  SYSCTRL_LL_Driver
  * @brief    SYSCTRL LL external configuration structure definition
  *
@verbatim   
  ===============================================================================
                                Exported Struct
  ===============================================================================  

    Exported Struct mainly extracts the SYSCTRL registers from the API, and abstracts 
    the structure. As long as it implements the low coupling between the registers 
    and the registers, the user only needs to configure the structure of the abstraction 
    layer and call hal_sysctrl_init. Function, you can configure the SYSCTRL module without 
    involving the configuration of the collective register.

@endverbatim
  *
  * @{
  */


/**
  * @}
  */

/** @defgroup SYSCTRL_LL_Interrupt SYSCTRL LL Interrupt Handle function
  * @brief   SYSCTRL LL Interrupt Handle function
  *
@verbatim   
  ===============================================================================
                        Interrupt Handle function
  ===============================================================================  

    This subsection provides a set of functions allowing to manage the SYSCTRL  
    Interrupt Handle function.

    how to use?

    The SYSCTRL interrupt handler uses a callback method that reserves the interface 
    to the user in the form of a callback function. The client needs to initialize 
    the callback function when initializing the SYSCTRL in order for the interrupt to 
    be processed normally. 
   
@endverbatim
  *
  * @{
  */



/**
  * @}
  */
  
/** @defgroup SYSCTRL_LL_Inti_Cfg SYSCTRL LL Initialization And Configuration
  * @brief    SYSCTRL LL Initialization And Configuration
  *
@verbatim   
  ===============================================================================
                        Initialization And Configuration
  ===============================================================================  

    This subsection provides a set of functions allowing to manage the SYSCTRL data 
    Initialization and Configuration.
    
    how to use?

@endverbatim
  *
  * @{
  */

/**
  * @brief  Enable the selected gpio port debounce.
  * @param  p_gpio: where x can be (A..C) to select the GPIO peripheral.
  * @param  gpio_pin: specifies the port bits to be written.
  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
  * @retval None.
  */
void ll_sysctrl_gpio_port_deb_en(GPIO_TypeDef* p_gpio, u16 gpio_pin);
/**
  * @brief  Disable the selected gpio port debounce.
  * @param  p_gpio: where x can be (A..C) to select the GPIO peripheral.
  * @param  gpio_pin: specifies the port bits to be written.
  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
  * @retval None.
  */
void ll_sysctrl_gpio_port_deb_dis(GPIO_TypeDef* p_gpio, u16 gpio_pin);
/**
  * @brief  Enable monitor which wake up group and Choose which edge to monitor.
  * @param  wkup_group: choose which wake up group to monitor. 
  *   This parameter can be any combination of LL_SYSCTRL_WKUP_x where x can be (0..11).
  * @param  wkup_edge: choose which edge to monitor.
  *   This parameter can be selected as LL_SYSCTRL_WKUP_RISING or LL_SYSCTRL_WKUP_FALLING.
  * @retval None.
  */
void ll_sysctrl_wkup_en_edge_sel(TYPE_ENUM_LL_WKUP wkup_group, TYPE_ENUM_LL_WKUP_EDGE wkup_edge);
/**
  * @brief swd disable 
  * @param None  
  * @note  if need using SWD pin as gpio, you need call this function to disable swd
  * @retval None  
  */
void swd_disable(void);
/**
  * @}
  */
  
/** @defgroup SYSCTRL_LL_Data_Transfers SYSCTRL LL Data transfers functions
  * @brief    SYSCTRL LL Data transfers functions 
  *
@verbatim   
  ===============================================================================
                            Data transfers functions
  ===============================================================================  

    This subsection provides a set of functions allowing to manage the SYSCTRL data 
    transfers and receive.
  
@endverbatim
  *
  * @{
  */




/**
  * @}
  */

/**
  * @}
  */

#ifdef __cplusplus
}
#endif

/**
  * @}
  */

/**
  * @}
  */

#endif //__JS32T031_LL_SYSCTRL_H

/*************************** (C) COPYRIGHT 2022 JUSHENG ***** END OF FILE *****/
